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HT47R10A-1/HT47C10-1 R-F Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0029E Using the Time Base Function in the HT47R20A-1 - HA0030E Using the RTC in the HT47R20A-1 - HA0034E Using the Buzzer Function in the HT47R20A-1 - HA0036E Using the PFD Function in the HT47R20A-1 - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * Low voltage reset circuit * Buzzer output * Power down and and wake-up functions reduce
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* Eight bidirectional I/O lines * Single external interrupt input * Single 16-bit programmable timer/event counter * On-chip crystal and RC oscillator for system clock * 32.768kHz crystal oscillator for real time clock or sys-
power consumption
* C type or R type LCD bias * LCD driver circuits with 102, 103 or 94 segments * Single channel RC type A/D converter * Two-level subroutine nesting * Bit manipulation instructions * 16-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock * All instructions executed within one or two machine
tem clock
* Watchdog Timer * 1K16 program memory * 328 data memory RAM * Real Time Clock (RTC) * 8-bit prescaler for RTC * Low voltage detector
cycles
* 63 powerful instructions * 44-pin QFP package
General Description
The HT47R10A-1/HT47C10-1 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for applications that interface directly to analog signals, such as those from sensors. The mask version HT47C10-1 device is fully pin and functionally compatible with the HT47R10A-1, OTP version device. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, RC type A/D Converter, LCD driver, Power Down and wake-up functions, enhance the versatility of these devices to suit a wide range of Resistor to Frequency application possibilities such as sensor signal processing, remote metering, industrial control, consumer products, subsystem controllers, etc.
Rev. 1.10
1
September 27, 2007
HT47R10A-1/HT47C10-1
Block Diagram
P A 5 /IN T M In te rru p t C ir c u it M U X T im e r A IN T C P ro g ra m EPROM P ro g ra m C o u n te r STACK U X T1 S y s te m RTC C lo c k
OSC
R T C O u tp u t P A 4 /T M R
T im e r B In s tr u c tio n R e g is te r
A /D C lo c k IN RC A /D Type C o n v e rte r CS CRT RT RS
MP
M U
X
D a ta M e m o ry
In s tr u c tio n D ecoder ALU
MUX
RTC W DT STATUS M U X
S Y S C L K /4 RTC OSC OSC3 OSC4
T im in g G e n e ra to r
S h ifte r P o rt A
W DT OSC
OSC2 OSC4
OS OS RE VD VS S
D
S
C1 C3
BP ACC LCD M e m o ry PA
C1 C2
H a lv e V o lta g e
PA0 PA1 PA2 PA4 PA5 PA6
/B Z /B Z ~PA3 /T M R /IN T ~PA7
L C D D r iv e r H ALT C O M 0~ COM2 C O M 3/ SEG9 SEG 0~ SEG8 E N /D IS
V1
V2 VLCD
L V D /L V R
Pin Assignment
C O M 3 /S E G 9
SEG2 SEG1 SEG0 V2 34 35 36 37 38 39 40 41 42 43 44 1 NC 2 3 4
VLCD V1
33 32 31 30 29 28 27 26 25 24 23
SEG4 SEG3
SE SE SE SE G8 G7 G6 G5
22 21 20 19 18 17 16 15 14 13 12
C2 C1
NC OSC4 OSC3
COM2 COM1 COM0 NC IN CS RS CRT RT VSS NC
H T 4 7 R 1 0 A -1 /H T 4 7 C 1 0 -1 4 4 Q F P -A
VDD OSC2 OSC1 RES
5
2
6
7
8 9
10 11
PA PA PA PA PA NC 4 /T M R 3 1 /B Z 0 /B Z
PA6 P A 5 /IN T
NC PA7
Rev. 1.10
2
September 27, 2007
HT47R10A-1/HT47C10-1
Pin Description
Pin Name PA0/BZ PA1/BZ PA2~PA3 PA4/TMR PA5/INT PA6~PA7 IN CS RS CRT RT COM0~COM2 COM3/SEG9 SEG0~SEG8 V1, V2, C1, C2 VLCD I/O Option Function Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. The buzzer, TMR and external interrupt input are pin-shared with PA0, PA1, PA4 and PA5 respectively. Oscillation input pin Reference capacitor connection pin Reference resistor connection pin Resistor/capacitor sensor connection pin Resistor sensor measurement connection pin
I/O
Pull-high Wake-up Buzzer
I O O O O O O 3/4 I
3/4
1/2, 1/3 or 1/4 COM3/SEG9 can be set as an LCD common or segment output driver by a Duty configuration option. COM0~COM2 are LCD panel plate outputs. 3/4 3/4 3/4 LCD panel segments driver outputs LCD voltage pump LCD power supply
OSC2 OSC1
O I
OSC1 and OSC2 are connected to an RC network or a external crystal, determined by configuration by option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 Crystal or RC frequency. If the system clock originates from the RTC oscillator, which is connected to OSC3 and OSC4, these two pins can be left floating. Real time clock oscillator. RTC or OSC3 and OSC4 are connected to a 32768Hz crystal oscillator or to a system System Clock clock source, determined by configuration option. 3/4 3/4 3/4 Schmitt trigger reset input, active low. Negative power supply, ground Positive power supply
OSC4 OSC3 RES VSS VDD
O I I 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
3
September 27, 2007
HT47R10A-1/HT47C10-1
D.C. Characteristics
Test Conditions Symbol Parameter VDD VDD VLCD IDD1 Operating Voltage LCD Power Supply (Note*) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (fSYS=32768Hz) 3/4 3/4 3V 5V 5V 3V 5V ISTB1 Standby Current (*fS=fSYS/4) 3V 5V ISTB2 Standby Current (*fS=RTC OSC) 3V 5V ISTB3 Standby Current (*fS=WDT RC OSC) 3V 5V 3V ISTB4 Standby Current (*fS=RTC OSC) 5V 3V ISTB5 Standby Current (*fS=RTC OSC) 5V 3V ISTB6 Standby Current (*fS=WDT RC OSC) 5V 3V ISTB7 Standby Current (*fS=WDT RC OSC) 5V VIL1 VIH1 VIL2 VIH2 IOL1 Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) I/O Port Sink Current 5V IOH1 3V I/O Port Source Current 5V IOL2 3V LCD Common and Segment Current 5V VOL=0.1VA VOH=0.9VDD 3/4 3/4 3/4 3/4 3V VOL=0.1VDD No load, fSYS=8MHz No load, LCD on, C type LVR and LVD disable No load, system HALT, LCD off at HALT No load, system HALT, LCD on at HALT, C type No load, system HALT LCD on at HALT, C type No load, system HALT, LCD on at HALT, R type, 1/2 bias No load, system HALT, LCD on at HALT, R type, 1/3 bias No load, system HALT, LCD on at HALT, R type, 1/2 bias No load, system HALT, LCD on at HALT, R type, 1/3 bias 3/4 3/4 3/4 3/4 Conditions fSYS=4MHz fSYS=8MHz VA5.5V No load, fSYS=4MHz 2.2 3.3 2.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 6 10 -2 -5 210 350 3/4 3/4 3/4 1 2.5 4 40 80 3/4 3/4 2.5 10 2 6 17 34 13 26 14 28 10 26 3/4 3/4 3/4 3/4 12 25 -4 -8 420 700 5.5 5.5 5.5 2 5 8 80 160 1 2 5 20 5 10 30 60 25 50 25 50 20 40 0.3VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 3/4 3/4 V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V mA mA mA mA mA mA Min. Typ. Max. Unit Ta=25C
IDD2
IDD3
Rev. 1.10
4
September 27, 2007
HT47R10A-1/HT47C10-1
Test Conditions Symbol Parameter VDD IOH2 LCD Common and Segment Current Pull-high Resistance of I/O Ports and INT Low Voltage Reset Low Voltage Detector Voltage 3V 5V 3V 5V 3/4 3/4 Conditions VOH=0.9VA -80 -180 20 10 2.7 3.0 -160 -360 60 30 3.0 3.3 3/4 3/4 100 50 3.3 3.6 mA mA kW kW V V Min. Typ. Max. Unit
RPH VLVR VLVD Note:
3/4
* for the value of VA refer to the LCD driver section. *fS please refer to WDT clock option
A.C. Characteristics
Test Conditions Symbol Parameter VDD fSYS1 System Clock (Crystal OSC, RC OSC) System Clock (32768Hz Crystal OSC) 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V tRES tSST tLVR tINT Note: External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width *tSYS=1/fSYS1, 1/fSYS2 3/4 3/4 3/4 3/4 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 3/4 3/4 400 400 3/4 3/4 0 0 45 32 1 3/4 0.25 1 3/4 3/4 32768 32768 3/4 3/4 90 65 3/4 1024 1 3/4 4000 8000 3/4 3/4 4000 8000 180 130 3/4 3/4 2 3/4 Min. Typ. Max.
Ta=25C Unit kHz kHz Hz Hz kHz kHz ms ms ms tSYS ms ms
fSYS2
fRTCOSC RTC Frequency fTIMER Timer I/P Frequency
tWDTOSC Watchdog Oscillator Period
Rev. 1.10
5
September 27, 2007
HT47R10A-1/HT47C10-1
Functional Description
Execution Flow The microcontroller system clock is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in the program memory are executed and its contents specify a maximum of 1024 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2
incremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the PC manipulates the program transfer by loading the address corresponding to each instruction. A conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise it will proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k
T3
T4
T1
T2
T3
T4
In s tr u c tio n C lo c k PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter Mode *9 Initial reset External interrupt Timer/event counter interrupt RTC interrupt Skip Loading PCL Jump, call branch Return from subroutine *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0
Program Counter+2 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *9~*0: Program counter bits S9~S0: Stack register bits #9~#0: Instruction code bits @7~@0: PCL bits
Rev. 1.10
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September 27, 2007
HT47R10A-1/HT47C10-1
Program Memory The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 102416 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
000H 004H 008H 00C H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e R T C In te r r u p t S u b r o u tin e P ro g ra m M e m o ry
n00H nFFH
L o o k - u p T a b le ( 2 5 6 W o r d s )
This area is reserved for the initialisation program. After a chip reset, the program always begins execution at location 000H.
* Location 004H
3FFH
L o o k - u p T a b le ( 2 5 6 W o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to 3
This area is reserved for the external interrupt service program. If the INT interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
Program Memory can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to executing the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depending upon requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organised into two levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. During a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented using the RET or RETI instructions, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use Table Location
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a Timer/Event Counter A or B overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
This area is reserved for the real time clock interrupt service program. If a real time clock interrupt results from a real time clock overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Table location
Any location in the Program Memory space can be used as a look up table. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word is transferred to the TBLH register. The table higher-order byte register, TBLH, is read only. The TBLP table pointer register is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH register is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR and errors Instruction(s) TABRDC [m] TABRDL [m]
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *9~*0: Table location bits P9~P8: Current program counter bits 7 @7~@0: Table pointer bits
Rev. 1.10
September 27, 2007
HT47R10A-1/HT47C10-1
the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow will occur and the first entry will be lost. Only the most recent two return addresses are stored. Data Memory - RAM The data memory has a 528 bit structure. The data memory is divided into two functional groups: special function registers and general purpose data memory (328). Most are read/write, but some are read only. The special function registers include the indirect addressing register 0 (00H), the memory pointer register 0 (mp0; 01H), the indirect addressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer (BP;04H), the accumulator (ACC;05H), the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the real time clock control register (RTCC;09H), the status register (STATUS;0AH), the interrupt control register (INTC;0BH), the I/O registers (PA;12H), the I/O control registers (PAC;13H), the Timer/Event Counter A higher order byte register (TMRAH;20H), the Timer/Event Counter A lower order byte register (TMRAL;21H), the Timer/Event Counter control register (TMRC;22H), the Timer/Event Counter B higher order byte register (TMRBH;23H), the Timer/Event Counter B lower order byte register (TMRBL;24H), and the RC oscillator type A/D converter control register (ADCR; 25H). The remaining space before the 60H are reserved for future expanded usage and reading these location will return the result 00H. The general purpose data memory, addressed from 60H to 7FH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instruction, respectively. They are also indirectly accessible through memory pointer registers (MP0;01H, MP1;03H). Indirect Addressing Register Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indirect addressing registers are not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers which can be used to access the data memory in combination with their corresponding indirect addressing registers.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 60H G e n e ra l P u rp o s e D a ta M e m o ry (3 2 B y te s ) 7FH TM RAH TM RAL TM RC TM RBH TM RBL ADCR PA PAC S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C
:U nused
R e a d a s "0 0 "
RAM Mapping (Bank 0)
MP0 can be applied only to data memory, while MP1 can be applied to data memory and the LCD display memory. Accumulator The accumulator is related to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. The data movement between two data memory locations must pass through the accumulator.
Rev. 1.10
8
September 27, 2007
HT47R10A-1/HT47C10-1
Arithmetic and Logic Unit - ALU The ALU performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
Interrupts The HT47R10A-1/HT47C10-1 provides an external interrupt, an internal timer/event counter interrupt and an internal real time clock interrupt. The interrupt control register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. When an interrupt subroutine is serviced, all other interrupts will be blocked by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval, but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then by branching to subroutines at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the accumulator and status register are altered by the interrupt service program, this may corrupt the desired control sequence, therefore their contents must be saved first. An external interrupt is triggered by a high to low transition on the INT pin and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag, EIF, and EMI bits, will be cleared to disable other interrupts.
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by the Watchdog Timer overflow, system power-up, clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Bit No. 0 Label C
Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 STATUS (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
Rev. 1.10
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HT47R10A-1/HT47C10-1
Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ETI ERTI EIF TF RTF 3/4 Function Master (global) interrupt enable (1= enable; 0= disable) External interrupt enable (1= enable; 0= disable) Timer/event counter interrupt enable (1= enable; 0=disable) Real time clock interrupt enable (1= enable; 0= disable) External interrupt request flag (1= active; 0= inactive) Timer/event counter request flag (1= active; 0= inactive) Real time clock request flag (1= active; 0= inactive) Unused bit, read as 0 INTC (0BH) Register The internal timer/event counter interrupt is initialised by setting the timer/event counter interrupt request flag (TF; bit 5 of the INTC), caused by a Timer A or Timer B overflow. When the interrupt is enabled, and the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag, TF, will be reset and the EMI bit cleared to disable further interrupts. The real time clock interrupt is initialised by setting the real time clock interrupt request flag (RTF; bit 6 of the INTC), caused by a regular real time clock signal. When the interrupt is enabled, and the stack is not full and the RTF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag, RTF, will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter Interrupt Real Time Clock Interrupt Priority 1 2 3 Vector 04H 08H 0CH The external interrupt request flag (EIF), real time clock interrupt request flag (RTF), timer/event counter request flag (TF), enable external interrupt bit (EEI), enable real time clock interrupt bit (ERTI), enable timer/event counter interrupt bit (ETI), and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ETI and ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (RTF, TF, EIF) are set, they remain in the INTC respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left, and enabling the interrupt is not well controlled, a CALL subroutine, if executed in the interrupt subroutine, will damage the original control sequence. Oscillator Configuration The HT47R10A-1/HT47C10-1 provides three oscillator circuits for system clocks, i.e., an RC oscillator, a crystal oscillator and a 32768Hz crystal oscillator, determined by configuration options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signals to conserve power. The 32768Hz crystal system oscillator still runs during the Power Down mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator will not be stopped; however instruction execution will cease. Since the 32768Hz crystal
OSC1 OSC1
OSC3
OSC4 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r
OSC2 C r y s ta l O s c illa to r
fS
YS
/4
YS
OSC2 /4 N M O S O p e n D r a in
O S C 2 : fS
System Oscillator Rev. 1.10 10 September 27, 2007
HT47R10A-1/HT47C10-1
oscillator (used as system oscillator or RTC oscillator) is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the Power Down mode. If the RC oscillator is used, an external resistor between OSC1 and ground is required, whose range should be between 24kW and 1MW. A frequency equal to the system clock divided by 4, is available on OSC2, which can be used for synchronisation purposes. As this is an open drain output, a pull-high resistor is required. The RC oscillator provides the most cost effective solution, however as its frequency of oscillation may vary with VDD, temperature and process variations, it is therefore not suitable for timing sensitive operations where accurate oscillator frequencies are desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for oscillation, and no other external components are required. A resonator may be connected between OSC1 and OSC2 instead of the crystal to get a frequency reference, but two external capacitors connected between OSC1, OSC2 and ground are required. Another oscillator circuit is designed for the real time clock, which has a fixed frequency of 32.768kHz. A 32.768kHz crystal should be connected between OSC3 and OSC4 for this function. The RTC oscillator circuit can be controlled to start up quickly by clearing the QOSC bit, which is bit 4 in the RTCC register. At power on this bit will be low, allowing for fast start up, but it is recommended to set it high after around 2 seconds to conserve power. The WDT oscillator is a free running on-chip RC oscillator, requiring no external components. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power. Watchdog Timer - WDT The WDT (fS) clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) or a real time clock oscillator
S y s te m C lo c k /4 O p tio n fS D iv id e r fS /2
8
(RTC oscillator), determined by configuration options. The timer is designed to prevent software malfunctions or a sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, any instructions related to the WDT will result in no operation. If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the HALT instruction is executed, the WDT will stop counting and lose its protecting purpose. When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since a HALT can stop the system clock. The WDT overflow under normal operation will initialise a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialise a warm reset in which only the Program Counter and Stack Pointer are reset to 0. To clear the WDT contents, three methods are adopted, an external reset (a low level to the RES pin), software instruction, or a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR WDT1 is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the WDT. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. The WDT time-out period ranges from 215/fS~216/fS since the clear Watchdog Timer instructions only clears the last two-stages of the WDT.
RTC O SC 32768H z W DT 12kH z OSC
W DT P r e s c a le r O p tio n W D T C le a r CK R T CK R T
T im e 2 15/fS ~ 2 14/fS ~ 2 13/fS ~ 2 12/fS ~
ou 21 21 21 21
tR eset 6/f S 5/f S 4/f S 3/f S
Watchdog Timer
Rev. 1.10
11
September 27, 2007
HT47R10A-1/HT47C10-1
Multi-function Timer The HT47R10A-1/HT47C10-1 provides a multi-function timer for the WDT, time base and real time clock but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source being sourced from the WDT OSC, RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranging from fS/22 to fS/28) for the LCD driver circuits, and a selectable frequency signal, ranging from fS/22 to fS/29, for the buzzer output chosen via configuration options. For proper LCD operation it is recommended to select a frequency as near as possible to 4kHz for the LCD driver circuits. Real Time Clock - RTC The real time clock or RTC operates in the same manner as the time base in that it is used to supply a regular internal interrupt. Its time-out period has a range between fS/28 to fS/215 whose actual value is chosen by software programming. Writing data to the RT2, RT1 and RT0 bits in the RTCC register, will provide various time-out periods. If an RTC time-out occurs, the related interrupt request flag, RTF- bit 6 of the INTC register, will be set. However if the interrupt is enabled, and the stack is not full, a subroutine call to location 0CH occurs. The real time clock time-out signal can also be utilised as a timer/event counter clock source, in order to get longer time-out periods. RT2 0 0 0 0 1 1 1 1 Note:
fS
Power Down Operation - HALT The Power Down mode is initialised by the HALT instruction and results in the following.
* The system oscillator will be turned off but the WDT
oscillator or RTC oscillator keeps running, if the WDT oscillator or the real time clock is selected.
* The contents of the on-chip RAM and registers remain
unchanged.
* The WDT will be cleared and will resume counting, if
the WDT clock source is the WDT oscillator or the real time clock oscillator.
* All I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared. * The LCD driver keeps running if the appropriate Con-
figuration option is chosen and if the WDT OSC or RTC OSC is selected. The system can leave the Power Down mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow executes a warm reset. By examining the TO and PDF flags, the reason behind the chip reset can be determined. The PDF flag is cleared during a system power-up or executing a Clear Watchdog Timer instruction and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, it causes a wake-up that only resets the Program Counter and SP, the others maintain their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by a configuration option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 system clock periods before normal operation is resumed. In other words, a dummy period will be inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by one more cycle. If the wake-up results in the next instruction execution, it will be executed immediately after the dummy period has finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power Down mode.
RT1 0 0 1 1 0 0 1 1
RT0 0 1 0 1 0 1 0 1
Clock Divided Factor 2* 29* 210* 211* 212 213 214 215
8
* not recommended for use
D iv id e r RT2 RT1 RT0 fS /2
8
P r e s c a le r fS /2 ~ fS /2 R T C In te rru p t
8 15
8 to 1 M ux.
Real Time Clock
Rev. 1.10
12
September 27, 2007
HT47R10A-1/HT47C10-1
Reset
* There are three ways in which a reset may occur. * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
VDD RES S S T T im e - o u t C h ip R e s e t tS
ST
The WDT time-out during HALT is different from other chip reset conditions, since it performs a warm reset that only resets the Program Counter and Stack Pointer leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different kinds of chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Reset Timing Chart
V
DD
V
DD
0 .0 1 m F 100kW RES 0 .1 m F B a s ic Reset C ir c u it 10kW 0 .1 m F 100kW RES H i-n o is e Reset C ir c u it
Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit.
Note: u means unchanged. To guarantee that the system oscillator has started and stabilised, the SST (System Start-up Timer) provides an extra delay. There is an extra delay of 1024 system clock pulses when the system awakes from the Power Down mode or when the system powers up. The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler, Divider WDT, RTC Timer/Event Counter Input/output ports Stack Pointer 000H Disabled Cleared Clear. After master reset, begin counting Off Input mode Points to the top of the stack
OSC1
HALT W DT RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n W DT T im e - o u t R eset E x te rn a l
W a rm
R eset
C o ld R eset
Reset Configuration
Rev. 1.10
13
September 27, 2007
HT47R10A-1/HT47C10-1
The registers states are summarised in the following table: Register MP0 MP1 BP ACC Program Counter TBLP TBLH RTCC STATUS INTC PA PAC TMRAH TMRAL TMRC TMRBH TMRBL ADCR Note: Reset (Power-on) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 000H xxxx xxxx xxxx xxxx --00 0111 --00 xxxx -000 0000 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 * refers to warm reset u means unchanged x means unknown There are six registers related to the timer/event counter operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR ([25H]). Reading and writing to the timer/event counter must be conducted in a specific way. It is important to note that writing to the TMRBL register only writes the data into a low byte buffer and not into the timer preload register. However writing to the TMRBH register will write the high byte data, as well as the contents of the low byte buffer, into the time/event counter preload register simultaneously. The timer/event counter preload register is therefore only modified by TMRBH write operations, while TMRBL write operations keep the timer/event counter preload register unchanged. Reading the TMRAH register will also latch the TMRAL data into the low byte buffer to avoid false timing problems. Reading the TMRAL only returns the contents of the low byte buffer. In other words, the low byte of the timer/event counter cannot be read directly. It must be read by first reading the TMRAH register first to transfer the low byte contents of the timer/event counter into the buffer. WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu uuuu uuuu --00 0111 --1u uuuu -000 0000 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu uuuu uuuu --00 0111 --uu uuuu -000 0000 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 RES Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu uuuu uuuu --00 0111 --01 uuuu -000 0000 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 1xxx --00 WDT Time-out (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H* uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu --uu
Timer/Event Counter One 16-bit timer/event counter or one single channel RC type A/D converter is implemented in the HT47R10A-1/HT47C10-1. The ADC/TM bit, which is bit 1 of the ADCR register, determines whether Timer A and Timer B is composed of one 16-bit timer/event counter or Timer A and Timer B is composed of a single channel RC type A/D converter. The TMRAL, TMRAH, TMRBL, TMRBH registers constitute one 16-bit timer/event counter, when the ADC/TM bit is 0. The TMRBL and TMRBH registers are timer/event counter preload registers for the lower-order byte and higher-order byte respectively. Using the internal clock, there are three reference time bases. The timer/event counter internal clock source may come from the system clock/RTC OSC, the system clock/4 or the RTC time-out signal to generate an accurate time base. Using an external clock input allows external events to be counted, to count external RC type A/D clocks, measure time intervals or pulse widths or to generate an accurate time base.
Rev. 1.10
14
September 27, 2007
HT47R10A-1/HT47C10-1
If the timer/event counter is running, the TMRAH, TMRAL, TMRBH and TMRBL registers cannot be read or written to. To avoid an overlap between Timer A and Timer B, the TMRAH, TMRAL, TMRBH and TMRBL registers should be accessed with the MOV instruction when the timer is not running. The TMRC register is the timer/event counter control register, which defines the timer/event counter options. The timer/event counter control register defines the operating mode, counting enable or disable and the active edge. Writing to Timer B places the timer start value into the timer/event counter preload register, while reading Timer A provides the contents of the timer/event counter. Timer B is a timer/event counter preload register. The TM0, TM1 and TM2 bits define the operation mode. The event count mode is used to count external events, which are sourced on the external pin, TMR. The A/D clock mode is used to count external A/D clocks, the RC oscillation mode is determined by the ADCR register. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to measure the high or low level duration of an external signal on pin TMR. The counting is based on the instruction clock.
S y s te m C lo c k /R T C O S y s te m C lo A /D C RTC S ck lo O C /4
In the event counting mode, the A/D clock or internal timer mode, once the timer/event counter starts counting, it will count from its current contents in the timer/event counter (TMRAH and TMRAL) to FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload registers, TMRBH and TMRBL, and at the same time generates a corresponding interrupt request flag, which is TF, bit 5 in the INTC register. In the pulse width measurement mode, with the TON and TE bits equal to 1, once the TMR pin has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the TMR pin returns to its original level and resets the TON bit. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be made. The TON bit has to be set again by the program if further measurements are to be made. Note that in this operation mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues an interrupt request just like the other three modes. To enable the counting operation, the timer TON bit, should be set to 1. In the pulse width measurement
ck ut M U X
D a ta B u s 1 6 - b it T im e r A O v e r flo w In te rru p t
TM R TE TM TM TM TO N 2 1 0 P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 - b it T im e r B TM 2 TM 1 TM 0
R e lo a d
Timer/Event Counter Bit No. 0~2 3 4 Label 3/4 TE TON Unused bit, read as 0 Defines the TMR active edge of the timer/event counter (0=active on low to high edge; 1=active on high to low edge) Enable or disable timer counting (0=disable; 1=enable) Defines the operating mode (TM2, TM1, TM0) 000=Timer mode (system clock/RTC OSC). The system clock or RTC OSC is selected as the timer source by configuration option. 001=Timer mode (system clock/4) 010=Timer mode (RTC output) 011=A/D clock mode (RC oscillation decided by ADCR register) 100=Event counter mode (external clock) 101=Pulse width measurement mode (system clock/4) 110=Unused 111=Unused TMRC (22H) Register Rev. 1.10 15 September 27, 2007 Function
5 6 7
TM0 TM1 TM2
HT47R10A-1/HT47C10-1
mode, TON will be automatically cleared after the measurement cycle is completed. But in the other three modes, the TON can only be reset by instructions. The timer/event counter overflow is one of the wake-up sources. If the timer/event counter is not running, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter preload register is kept only in the timer/event counter preload register. The timer/event counter will continue to operate normally until an overflow occurs, at which point the new data will be transferred to the timer. When the timer/event counter (reading TMRAH) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must be taken into consideration by the programmer. It is strongly recommended to load first the desired value for TMRBL, TMRBH, TMRAL, and TMRAH registers, before turning on the related timer/event counter to ensure proper operation. This is because the initial values of TMRBL, TMRBH, TMRAL and TMRAH are unknown. If the timer/event counter is on, the TMRAH, TMRAL, TMRBH and TMRBL registers cannot be read or written to. Only when the timer/event counter is off and when the instruction MOV is used can these four registers be read or written to.
Timer/event counter mode example (disable interrupt): clr tmrc clr adcr.1 clr intc.5 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a mov a, 00110000b mov tmrc, a p10: clr wdt snz intc.5 jmp p10 clr intc.5 ; set timer mode ; clear timer/event counter interrupt request flag ; give timer initial value ; count 1000 time and then overflow
; timer clock source is fSYS/4 and timer on
; polling timer/event counter interrupt request flag ; clear timer/event counter interrupt request flag ; program continue
Rev. 1.10
16
September 27, 2007
HT47R10A-1/HT47C10-1
A/D Converter A single channel RC type A/D converter is implemented in the HT47R10A-1/HT47C10-1. The A/D converter contains two 16-bit programmable count-up counters. The Timer A clock source is sourced from the system clock/RTC OSC, instruction clock or RTC output. The Timer B clock source is sourced from the external RC oscillator. The TMRAL, TMRAH, TMRBL, TMRBH registers will form an A/D converter when the ADC/TM, which is bit 1 of the ADRC register, is set to 1. The A/D converter Timer B clock source may come from the IN external clock input pin, RS~CS oscillation, RT~CS oscillation, CRT~CS oscillation (CRT is a resistor). The Timer A clock source is sourced from the system clock/RTC OSC, instruction clock or RTC prescaler clock output determined by the TMRC register. There are six registers related to the A/D converter, i.e., TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR. The internal timer clock is the input to TMRAH and TMRAL, the A/D clock is the input to TMRBH and TMRBL. The OVB/OVA bit, which is bit 0 of the ADCR register, decides whether Timer A overflows or Timer B overflows. When this occurs, the TF bit is set and a timer interrupt occurs. When the A/D converter mode Timer A or Timer B overflows, the TON bit is reset and the timer stops counting. Writing to TMRAH/TMRBH places the s t a r t v a l u e i n Ti m e r A / Ti m e r B a n d r e a d i n g TMRAH/TMRBH retrieves the contents of Timer A/Timer B. Writing to TMRAL/TMRBL only writes the data into a low byte buffer. Writing to TMRAH/TMRBH will write the data and the contents of the low byte buffer into the Timer A/Timer B (16-bit) simultaneously. The Ti m e r A / Ti m e r B i s c h a n g e d b y w r i t i n g t o TMRAH/TMRBH operations while writing to TMRAL/TMRBL operations will keep Timer A/Timer B unchanged. Bit No. Label Reading TMRAL/TMRBH will also latch TMRAL/TMRBL into the low byte buffer to avoid false timing problems. Reading TMRAL/TMRBL only returns the contents of the low byte buffer and not the actual timer value. Therefore the low byte of Timer A/Timer B cannot be read directly. It must first read TMRAH/TMRBH to transfer the low byte contents of Timer A/Timer B into the buffer. If the A/D converter Timer A and Timer B are counting, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. To avoid an overlap between Timer A and Timer B, the TMRAH, TMRAL, TMRBH and TMRBL registers should be accessed with the MOV instruction when Timer A and Timer B are not running. Bits 4~7 of the ADCR register decides which resistor and capacitor comprise an oscillation circuit and input to TMRBH and TMRBL. The TM0, TM1 and TM2 bits of TMRC define the Timer A clock source. It is recommended that the clock source of Timer A uses the system clock/RTC OSC, instruction clock or the RTC prescaler clock. If the TON bit is set to 1 then Timer A and Timer B will start counting until Timer A or Timer B overflows. The timer/event counter will then generate an interrupt request flag, TF - bit 5 of INTC, and the Timer A and Timer B will stop counting and reset the TON bit to 0 at the same time. If the TON bit is 1, TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event counter is off and when the instruction MOV is used can these four registers be read or written to.
Function In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt which comes from Timer A overflow or Timer B overflow. (0= Timer A overflow; 1= Timer B overflow) In the timer/event counter mode, this bit is void. Defines 16 timer/event counters or RC type A/D converter is enabled. (0= timer/event counter enable; 1= A/D converter is enabled) Unused bit, read as 0. Defines the A/D converter operating mode (M3, M2, M1, M0) 0000= IN external clock input mode 0001= RS~CS oscillation (reference resistor and reference capacitor) 0010= RT~CS oscillation (resistor sensor and reference capacitor) 0011= CRT~CS oscillation (resistor sensor and reference capacitor) 0100= RS~CRT oscillation (reference resistor and sensor capacitor) 0101= Unused mode 0110= Unused mode 0111= Unused mode 1XXX= Unused mode ADCR (25H) Register
0
OVB/OVA
1 2~3
ADC/TM 3/4
4 5 6 7
M0 M1 M2 M3
Rev. 1.10
17
September 27, 2007
HT47R10A-1/HT47C10-1
RC type AD converter mode example (Timer A overflow): clr tmrc clr adcr.1 clr intc.5 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a mov a, 00010010b mov adcr,a mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00110000b mov tmrc, a p10: clr wdt snz intc.5 jmp p10 clr intc.5 ; set timer mode ; clear timer/event counter interrupt request flag ; give Timer A initial value ; count 1000 time and then overflow
; RS~CS; set RC type ADC mode; set Timer A overflow ; give Timer B initial value
; Timer A clock source is fSYS/4 and timer on
; polling timer/event counter interrupt request flag ; clear timer/event counter interrupt request flag ; program continue
Example for RC type AD converter mode (Timer B overflow): clr tmrc clr adcr.1 clr intc.5 mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00010011b mov adcr, a mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a mov a, 00110000b mov tmrc, a p10: clr wdt snz intc.5 jmp p10 clr intc.5 ; set timer mode ; clear timer/event counter interrupt request flag ; give Timer A initial value
; RS~CS; set RC type ADC mode; set Timer B overflow
; give Timer B initial value ; count 1000 time and then overflow
; Timer A clock source is fSYS/4 and timer on
; polling timer/event counter interrupt request flag ; clear timer/event counter interrupt request flag ; program continue
Rev. 1.10
18
September 27, 2007
HT47R10A-1/HT47C10-1
S1 S y s te m C lo c k /R T C O S C S2 S y s te m C lo c k /4 S3 R T C O u tp u t TON O V B /O V A = 1 T im e r B R esetTO N T im e r A O V B /O V A = 0 In te rru p t
S9
S4 IN CS
S5 CRT
S6
S7 RS
S8 RT
TN2 0 0 0 O th e r
TN1 0 0
TN0 0 1
S1 1 0
S2 0 1
S3 0 0
M3 0 0
M2 0 0
M1 0 0
M0 0 1
S4 0 1
S5 0 0
S6 0 0
S7 0 1
S8 0 0
S9 1 1
1
0 0
0 0
0 0
1 0 0
0 0 1
0 1 0
1 1 0
0 1 0 0
1 0 1 0
0 1 0 0
0 0 1 0
0 0 0 0
1 1
1 1 0
N o te : 0 = o ff, 1 = o n
O th e r N o te : 0 = o ff, 1 = o n
RC Type A/D Converter Input/Output Ports There are 8 bidirectional input/output lines in the microcontroller, confined into a single port known as PA, which is mapped to the data memory at [12H]. These I/O lines can be used for input and output operations. For input operation, these lines are non-latching, that is, these inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Port PA, has its own Port Control Register known as PAC, which controls the input/output configuration of each I/O line. With this control register, each I/O pin can be configured to be either a CMOS output or a Schmitt trigger input. Configuration options exist to connect pull-high resistors to the inputs. The I/O pins can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must be written with a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the pin will be setup as an output and the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For an output function, CMOS is the only configuration. These control register is mapped to locations 13H. After a chip reset,the I/Os default to an input condition and will remain at a high level, or floating state, depending upon the pull-high configuration options. Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O pin has a pull-high option where individual pull-high resistors can be connected to each pin. Note that a non- pull-high input will result in a floating state. The PA0, PA1, PA5, PA4 are pin-shared with BZ, BZ, INT, TMR pins, respectively.
Rev. 1.10
19
September 27, 2007
HT47R10A-1/HT47C10-1
V C o n tr o l B it Q D CK S Q P u ll- h ig h
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK S Q M U X
PA PA PA PA PA PA
0 /B 1 /B 2~P 4 /T 5 /IN 6~P
A3 MR T A7
Z
Z
W r ite D a ta R e g is te r
P A 0 /P A 1 B Z /B Z M U X R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly )
BZEN
O P0~O P7
IN T fo r P A 5 O n ly T M R fo r P A 4 O n ly
Input/Output Ports
The PA0 and PA1 are pin-shared with the BZ and BZ pinsl, respectively. If the BZ/BZ option is selected, the output signal, if PA0/PA1 are setup as outputs, will be the buzzer signal generated by the Multi-function timer. If setup as inputs these pins will retain their I/O operation status. Once the BZ/BZ option is selected, the buzzer output signals are controlled by the PA0/PA1 data register only. The PA0/PA1 I/O functions are shown below. PA0 I/O PA1 I/O PA0 Mode PA1 mode PA0 Data PA1 Data I I x x x x I O x C x D I D OOOOOOOO I I I OOOOO
CBBCBBBB x x x CCCBB 1 0 x 0 1 x B B
D0 x x
1 D0 0 B D0 0
x D1 D D B
PA0 Pad Status I PA1 Pad Status I Note:
D0 I I
I D1 D D 0
I input,O output, D, D0, D1 data B buzzer option, BZ or BZ, x dont care C CMOS output
configuration options select the LCD to have 94 segment outputs, then the 49H address area of the LCD display memory cannot be accessed. The LCD data memory area is located from 40H to 49H in Bank 1of the Data Memory. The bank pointer, BP- located at 04H of the data memory, will switch between the general purpose data memory and the LCD display memory. When the BP is set to the value 01H any data written into the area 40H~49H will effect the LCD display. Data must be written indirectly using MP1. When BP is cleared to 00H, any data written into the area 40H~49H will access the general purpose data memory. The LCD display memory can be read and written to only using the indirect addressing mode via MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the HT47R10A-1/HT47C10-1.
COM 0 1 2 3 3 2 40H 41H 42H 43H 47H 48H 49H B it 0 1
It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power if in floating input states. LCD Display Memory The HT47R10A-1/HT47C10-1 provides an area of embedded data memory for the LCD display. The LCD display memory has a structure of 104 bits. Note that if the
SEGMENT
0
1
2
3
7
8
9
Display Memory (Bank 1)
Rev. 1.10
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September 27, 2007
HT47R10A-1/HT47C10-1
LCD Driver Output The LCD output number of the HT47R10A-1/ HT47C10-1 LCD driver can be 102, 103 or 94, the choice of which is chosen via a configuration option, i.e., 1/2 duty, 1/3 duty or 1/4 duty. The bias type of the LCD driver can be C- type or R- type. For C-type biasing, a capacitor connected between C1
D u r in g a r e s e t p u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o r m a l o p e r a tio n m o d e
and C2 pins is needed. The bias voltage of the LCD driver can be either 1/2 bias or 1/3 bias, chosen via a configuration option. If 1/2 bias is selected, a capacitor mounted between the V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed on each of the V1 and V2 pins. Refer to the application diagram. If the R bias type is selected, no external capacitors are required.
VA
VB VSS VA VB VSS
*
*
*
COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e lig h te d HALT M ode C O M 0 ,C O M 1 ,C O M 2 * A ll L C D N o te : d r iv e r o u tp u ts is u s e d .
VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS S VA
S
S S S S S S S S S
" * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D V A = V L C D , V B = 1 /2 V L C D
VB VSS VA VB VSS
LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)
Rev. 1.10
21
September 27, 2007
HT47R10A-1/HT47C10-1
VA COM0 VB VC VSS VA VB COM1 VC VSS VA COM2 VB VC VSS VA VB COM3 VC VSS VA L C D s e g m e n ts O N C O M 2 s id e lig h te d VB VC VSS N o te : 1 /4 d u ty , 1 /3 b ia s , C 1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D ty p e : "V A " V L C D , "V B " 2 /3 V L C D , "V C " 1 /3 V L C D
LCD Driver Output
Low Voltage Reset/Detector Functions There is a low voltage detector, LVD, and a low voltage reset circuit, LVR, implemented in the microcontroller. These two functions can be enabled/disabled by configuration options. Once the configuration options for the LVD is enabled, bit RTCC.3 can be used to enable or disable the LVD circuit. The LVD detector status can be monitored via bit RTCC.5. The LVR has the same effect or function as the external RES signal which performs a chip reset. During the Power Down mode the LVR is disabled.
1 /3 b ia s C1 C2 V1 1 /2 b ia s C1 C2 V1 V VLCD V2 V
VLCD V2
DD
DD
V1, V2, VLCD Application Diagram C Type)
Rev. 1.10
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September 27, 2007
HT47R10A-1/HT47C10-1
The RTCC register definitions are listed in the following table. Bit No. 0~2 3 4 5 6~7 Label RT0~RT2 LVDC* QOSC LVDO 3/4 Read/Write R/W R/W R/W R 3/4 Function 8 to 1 multiplexer control inputs to select the real time clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillating function 0/1: quick/slow start LVD detection output (1/0) 1: low voltage detected Unused bit, read as 0 RTCC (09H) Register
Buzzer The Buzzer function provides a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ pins form a complimentary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option is used to select from one of the three buzzer options. The first option is for both pins PA0 and PA1 to be used as normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins, the third option selects only the PA0 pin to be used as a BZ buzzer pin with the PA1 pin retaining its normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which when together generate a differential output that can supply more power to connected interfaces such as buzzers. The buzzer is driven by the internal clock source, fS, which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from fS/22 to fS/29. The clock source that generates fS, which in turn controls the buzzer frequency, can originate from three different sources, the RTC oscillator, the WDT oscillator or the system clock/4, the choice of which is determined by the fS clock source configuration option. It is important to note that if the RTC oscillator is selected as the system clock, then fS, and correspondingly the buzzer, will also have the RTC oscillator as its clock source. Note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock fS and the internal division ratio. There are no internal registers associated with the buzzer frequency. If the configuration options have selected both pins PA0 and PA1 to function as a BZ and BZ complementary pair of the buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low, both pins PA0 and PA1 will remain low. In this way the single bit PA0 of the PA register can be used as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA1 data bit in the PA register has no control over the BZ buzzer pin PA1. If configuration options have selected that only the PA0 pin is to function as a BZ buzzer pin, then the PA1 pin can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be setup as an output by setting bit PAC0 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer output, if set low, pin PA0 will remain low. In this way the PA0 bit can be used as an on/off control for the BZ buzzer pin PA0. If the PAC0 bit of the PAC port control register is set high, then pin PA0 can still be used as an input even though the configuration option has configured it as a BZ buzzer output.
Rev. 1.10
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September 27, 2007
HT47R10A-1/HT47C10-1
PAC Register PAC0 0 0 0 0 1 1 1 PAC Register PAC1 0 0 1 1 0 0 1 PA Data Register PA0 0 1 0 1 1 0 x PA0/PA1 Pin Function Control Note: x stand for dont care D stand for data 0 or 1 Note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the configuration option selection and force the pin to always function as an input pin. This arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit.
In te r n a l C lo c k S o u r c e
PA Data Register PA1 x x x x x x x
Output Function PA0=0 PA1=0 PA0=BZ PA1=BZ PA0=0 PA1=Input line PA0=BZ PA1=Input line PA0=Input line PA1=BZ PA0=Input line PA1=0 PA0=Input line PA1=Input line
P A 0 D a ta B Z O u tp u t a t P A 0
P A 1 D a ta B Z O u tp u t a t P A 1 B u z z e r O u tp u t P in C o n tr o l
Note:
The above diagram shows the situation where both pins PA0 and PA1 are selected by configuration option to be BZ and BZ buzzer output pins. The Port Control Register of both pins must have already been setup as output. The data setup on pin PA1 has no effect on the buzzer outputs.
Rev. 1.10
24
September 27, 2007
HT47R10A-1/HT47C10-1
Option The following shows the various options in the HT47R10A-1/HT47C10-1. All these options should be defined in order to ensure having a properly functioning system. No. 1 2 3 Option OSC type selection. This option is to determine if an RC, a crystal oscillator or an RTC oscillator is chosen as system clock. Clock source selection for WDT, RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC. WDT enable or disable selection. WDT can be enabled or disabled. CLR WDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means that only if both of the CLR WDT1 and CLR WDT2 have been executed, then WDT can be cleared. Buzzer output frequency selection. There are eight types of frequency signals for the buzzer output: fS/22~fS/29. fS means the WDT clock source. Wake-up selection. This option defines the wake-up function activity. External I/O pins all have the capability to wake-up the chip from a HALT mode by a following edge. Pull-high selection. This option is to determine whether the pull-high resistance is viable or not on the each bits of PA. I/O pins share with other function selection. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. LCD common selection. There are three types of selection: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin COM3/SEG9 will be set as a common output. LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS means the WDT clock source. LCD on or LCD off at the HALT mode selection. The LCD can be enabled or disabled at the HALT mode. LVD enable or disable LVR enable or disable System clock or RTC OSC selection. The timer/event counter source is from system clock or from RTC OSC in timer mode, and Timer A source is from system clock or RTC OSC in the A/D mode.
4
5
6
7 8
9
10
11 12 13 14
Rev. 1.10
25
September 27, 2007
HT47R10A-1/HT47C10-1
Application Circuits
V
DD
VDD Reset C ir c u it RES 0 .1 m F VSS
CO M 0~CO M 3 SEG 0~SEG 8
LCD PANEL
100kW 0 .1 m F
VLCD C1 C2 V1
LCD
P o w e r S u p p ly
0 .1 m F
V
DD
470pF 0 .1 m F R
OSC
fS Y S /4 o p e n d r a in C1
OSC1 OSC2 OSC1
R C S y s te m O s c illa to r 24kW 32768H z 10pF
OSC3
V2 0 .1 m F
C r y s ta l/R e s o n a to r S y s te m O s c illa to r F o r R 1 , C 1 , C 2 s e e n o te
C2 OSC4 PA0~PA7 IN OSC C ir c u it OSC1 OSC2 CS RS CRT RT H T 4 7 R 1 0 A -1 /H T 4 7 C 1 0 -1 R1
OSC2
OSC1
OSC2
32 Os OS un
7 6 8 H z C ry s ta l S y s te m c illa to r C 1 a n d O S C 2 le ft c o n n e c te d
O S C C ir c u it
Note:
1. Crystal/resonator system oscillators For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. Reset circuit The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information.
Rev. 1.10
26
September 27, 2007
HT47R10A-1/HT47C10-1
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 1.10
27
September 27, 2007
HT47R10A-1/HT47C10-1
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
Rev. 1.10
28
September 27, 2007
HT47R10A-1/HT47C10-1
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.10
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September 27, 2007
HT47R10A-1/HT47C10-1
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Rev. 1.10
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HT47R10A-1/HT47C10-1
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.10
31
September 27, 2007
HT47R10A-1/HT47C10-1
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.10
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September 27, 2007
HT47R10A-1/HT47C10-1
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Rev. 1.10
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HT47R10A-1/HT47C10-1
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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HT47R10A-1/HT47C10-1
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT47R10A-1/HT47C10-1
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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HT47R10A-1/HT47C10-1
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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HT47R10A-1/HT47C10-1
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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HT47R10A-1/HT47C10-1
Package Information
44-pin QFP (1010) Outline Dimensions
C D G 23 I 34 22 F A B E 44 12 K 1 11 a J 33 H
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 13 9.9 13 9.9 3/4 3/4 1.9 3/4 3/4 0.73 0.1 0 Nom. 3/4 3/4 3/4 3/4 0.8 0.3 3/4 3/4 0.1 3/4 3/4 3/4 Max. 13.4 10.1 13.4 10.1 3/4 3/4 2.2 2.7 3/4 0.93 0.2 7
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
43
September 27, 2007

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